From 154a413090645bac5ba4587999484e41088f3f89 Mon Sep 17 00:00:00 2001 From: Keir Fraser Date: Mon, 21 Jun 2010 09:59:10 +0100 Subject: [PATCH] vmx: Fix bug in VMX VPMU fixed function PMC offset This is a minor fix to the calculation of bit-width of fixed function perfmon counters in Intel processors. Bits 5-12 of edx register should be calculated as (edx & 0x1fe0) >>5 instead of using 0x1f70. From: "John, Jaiber J" Signed-off-by: Keir Fraser --- xen/arch/x86/hvm/vmx/vpmu_core2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c b/xen/arch/x86/hvm/vmx/vpmu_core2.c index 4646600ca4..ce4fd2d43e 100644 --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c @@ -83,7 +83,7 @@ static int core2_get_bitwidth_fix_count(void) { u32 eax, ebx, ecx, edx; cpuid(0xa, &eax, &ebx, &ecx, &edx); - return ((edx & 0x1f70) >> 5); + return ((edx & 0x1fe0) >> 5); } static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index) -- 2.30.2